1. Field of the Invention
The present invention relates to an automatic gain controller (hereinunder referred to as "AGC") in which a digital filter having a complicated structure is dispensed with. The present invention also relates to a receiver using the AGC. The present invention also relates to a control signal generator suitable to the AGC. The present invention also relates to a reception power controller using the AGC. In addition, the present invention relates to a communication method using the receiver.
2. Description of the Prior Art
FIG. 33 shows the structure of a conventional AGC. The circuit shown in FIG. 33 is substantially disclosed in, for example, Japanese Patent Laid-Open No. Hei 5-75664.
A variable gain amplifier 10 amplifies a received signal and supplies the amplified signal to a demodulator 12. The demodulator 12 performs the quadrature-phase detection of the amplified received signal and outputs the complex baseband signal obtained to a baseband circuit (not shown) and a square-sum calculator 14. The complex baseband signal is composed of an in-phase component I and a quadrature-phase component Q. The square-sum calculator 14 calculates the square-sum of the in-phase component I and a quadrature-phase component Q, i.e., the instantaneous reception power p from the following formula: EQU p=I.sup.2 +Q.sup.2
A digital filter 16 obtains an average reception power by filtering the square sum. If it is assumed that the received signal is an MSK (Minimum Shift Keying) modulated signal, since the MSK modulated wave has a constant envelope level, the average reception power obtained by the digital filter 16 is stable and does not change rapidly. It is therefore possible to balance the feedback loop shown in FIG. 33 so that the reception power output from the variable gain amplifier 10 is constant irrespective of the reception power input to the variable gain amplifier 10 by controlling the gain on the basis of the average reception power obtained so as to decrease when the average reception power is large and increase when the average reception power is small. As a result, the power of the complex baseband signal output from the demodulator 12 becomes constant, so that the processing by the baseband circuit at the subsequent stage becomes stable.
The digital filter 16 has a structure such as that shown in FIG. 34. In FIG. 34, the instantaneous reception power p of an input series and the output of a delay element 20 are input to an adder element 18. The adder element 18 adds the instantaneous reception power p and the output of the delay element 20. The output of the adder element 18 is delayed by one sampling period T by the delay element 20, and the delayed output is multiplied by a tap coefficient by a multiplier element 22. Thereafter, the thus-obtained output is input again to the adder element 18. In this manner, the output series Y.sub.i obtained from the adder element 18 is a value obtained by filtering the instantaneous reception power p through a low pass filter, in other words, an average reception power as represented by the following formula: EQU y.sub.i =x.sub.i -by.sub.i-1
wherein i represents a time, x.sub.i an input series and -b a tap coefficient. The filter having this structure is called a first order infinite impulse response (first order IIR) filter.
The unit impulse response h.sub.i of the filter, that is, the output series y.sub.i of the digital filter 16 when the unit impulse is given as the input series x.sub.i when the time t=0 is shown in FIG. 35 on the assumption that b=-e.sup.-T/.tau. In other words, the unit impulse response h.sub.i is obtained by discretizing the unit impulse response of the analog CR filter of the time constant t in the time domain. The characteristic of the digital filter 16 can be changed by changing b.
A more general structure of the digital filter 16 is shown in FIG. 36. In FIG. 36, the input series to an adder element 24 and the output series from the adder element 24 have a multiplicity of bits, and each output series from the adder element 24 is delayed by a clock period T by each of a multiplicity of cascaded delay elements 28 to 33. Each of the output series from the delay elements 28 to 33 is multiplied by the tap coefficient by multiplier elements 34 to 40, and each of the output series from the multiplier elements 34 to 40 is added to the input series by the adder element 24. Each of the output series of the delay elements 28 to 33 is multiplied by the tap coefficient by multiplier elements 42 to 48, and each of the output series of the multiplier elements 42 to 48 is added to the output series from the adder element 24 by an adder element 26. In other words, the structure shown in FIG. 36 is that of an n-order IIR filter.
The AGC having the above-described structure, however, produces various problems when the dynamic range of a received signal is as wide as, for example, several ten dB. In the case of applying the above-described AGC to a received signal having a wide dynamic range, it is necessary to greatly increase the bit number of the input series x.sub.i of the digital filter 16, for example, to about several ten bits. In the filter having such a structure, the number of taps (tap number) becomes so large that when the filter is implemented as hardware, problems such as an increase in the circuit scale and an increase in power consumption are caused, and when the filter is implemented as software, problems such as a high processing load are caused.
The above-described AGC is suitable for use in a modulation system such as an MSK in which the envelope level of the modulated wave is constant, but it is not suitable to a modulation system such as a QPSK (Quadrature Phase Shift Keying) in which the envelope level of the modulated wave is not constant. If the AGC shown in FIG. 33 using a filter having a small number of taps as shown in FIG. 34 as the digital filter 16 is applied to the automatic gain control of a QPSK demodulated wave, the feedback loop from the demodulator 12 to the variable gain amplifier 10 via the square-sum calculator 14 and the digital filter 16 inconveniently oscillates. This is because the cut off frequency of the digital filter 16 is so high that when the envelope level changes, the component having a comparatively high frequency passes through the digital filter 16. If the AGC shown in FIG. 33 using a filter having a large number of taps as shown in FIG. 36 as the digital filter 16, is applied to the automatic gain control of a QPSK demodulated wave, the responsiveness of the feedback loop is deteriorated so much that the high-speed response required at the start of communication or the like is not realized. This is because the responsiveness of the digital filter 16 is deteriorated due to the low cut-off frequency of the digital filter 16.
FIG. 37 shows another conventional structure of the automatic gain controller substantially disclosed in Japanese Patent Laid-Open No. Hei 3-254510. In FIG. 37, an A/D converter 50 for converting the amplified received signal into the digital signal is provided. An amplitude converter 52 converts the digital signal into the absolute valve thereof, and a square-sum calculator 54 calculates the square sum of the absolute valve. Thus, the average reception power is obtained from the square-sum calculator 56. A control signal generator 56 generates the control signal for the variable gain amplifier 10 on the basis of the average reception power so that the deviation from the control target is cancelled and, hence, the feedback loop is balanced.
In this conventional structure, however, the long pull-in time is required when the deviation represented in dB has a positive value and the astable operation occurs when the deviation represented in dB has a negative value, because the average reception power represented by the linear scale is used for controlling the gain. For example, in the case that the target equals 100 as the linear scale, the levels represented as +3dB and -3dB on the logarithm scale are represented as 200 and 50 on the linear scale, respectively. In the prior art, since the linear scale is used, the absolute value of the control signal for cancelling the +3 dB deviation becomes 2 times as large as that for cancelling the -3 dB deviation. This causes the long pull-in time for the +3dB deviation and astable operation for the -3 dB deviation.
To overcome the problem, a log-converter or a log-amplifier may be provided between the control signal generator and the variable gain amplifier. However, providing the log-converter or the log-amplifier results in an enlarged and complicated circuit.